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  • How to change address structure of MIG IP VIVADOJanuary 5

    I am doing an experiment on Xilinx VC709 board which involves accessing the on board DDR3 SO-DIMM using Microblaze via UART port. The Xilinx MIG IP has ROW:BANK:COLUMN or BANK:ROW:COLUMN options for the address structure. I want to access the same me

  • Reset the configuration of FPGA without reprogrammingNovember 14

    I am doing an experiment on Xilinx VC709 board. The experiment involves removing and plugging in the DDR3 RAM while the FPGA is running. But every time I plug back the RAM I have to reprogram the FPGA. I am using JTAG to program the FPGA, which takes

  • What are the typical uses for a soft-processor such as MicroBlaze?October 13

    I know that the FPGA-DSP combination is typically used for high-end power electronics/ultrasound/MRI/etc. Is it possible for the soft-processor to fully replace the DSP even on lower-end FPGAs such as Spartan 3/6? Added: What would be the reason for

  • xiomodule.h no such file or directoryOctober 7

    I'm working with MircoBlaze_mcs core and implement simple GIO file from the tutorial but it gives error ( "xiomodule.h" No such file or directory )when I synthesize the project . I find it in the API documentation in the SDK Project Explorer, un

  • Check the value of FSL_M_Control in the MicroBlazeApril 23

    I wrote a hardware accelerator which communicates with a MicroBlaze over FSL. In the Microblaze C code I would like to use putfsl() in a loop until the hardware accelerator signals the MicroBlaze that it should exit the loop: while( <FSL_M_Control is

  • Problem using FSL with microblazeFebruary 7

    I want to pass some data from my verilog to my microblaze core in ISE 14.7. I was doing some research and it seemed like the FSL was the easiest way to go about this. What I did was create a peripheral with one 32b input and one 32b output of the FSL

  • How to get MicroBlaze running on Papilio ProApril 20

    I am new to the FPGA world, and there seems to be gazzilions of boards and FPGA vendors. I just bought the Papilio Pro, which is based on the Spartan 6 LX9, and although I can already bitstream basic VHDL designs, I was looking to install the MicroBl

  • Generating a MSS file at command-line?February 12

    Is there a way to generate a mss file from the exported SDK XML file at command-line? At the moment, I still have to open xsdk, generate a new hello world project to create the mss file. But I would like to generate the mss file with makefiles. -----

  • Designing with AC'97 - why does it not have a (FIFO) buffer?October 15

    The AC'97 codec seems to dominate the world of digital audio I/O but, what is weird is that it has neither interrupts nor buffers so that it is difficult to interface with a controller, which has other activities. The AC97 demands polling it periodic

  • FSL Bus Problem in Xilinx FPGA Data ReturnJuly 22

    I wrote a custom IP peripheral in Verilog and interfaced it to MicroBlaze, using a hardware co-processor option. I can see the peripheral connected on the System Design Diagram. Everything compiles and the build is successful. Now I can see on hypert

  • Is the Microblaze soft cpu better than the Cortex M3 soft cpuFebruary 16

    Is the Microblaze soft cpu better than the Cortex M3 soft cpu in terms of functionality? Given all the buzz about the ARM based processors, I was wondering if to implement an ARM processor on my FPGA or if I should stick to the Microblaze that comes

  • Microcontrollers: Can I perform floating point operations in a Microblaze controller?January 22

    I wonder if I could perform floating point operations in a Microblaze controller? Thank you to all posible answers with direct references to documentation or articles. --------------Solutions------------- Floating-point operations are available, see

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